DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 244

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 and 1: Backplane Clock Selects (BPCS1 and BPCS0)
Bit 0: Backplane Clock Enable (BPEN)
Note: The backplane clock settings in TR.CCR2 are only active for Port 1 and Port 2 in the DS33R41 register map
and correspond to the output pins BPCLK1 and BPCLK2, respectively.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Multiframe Sync Source (TMSS). Should be set = 0 only when transmit hardware signaling is
enabled.
Bit 6: Interrupt Disable (INTDIS). This bit is convenient for disabling interrupts without altering the various
interrupt mask register settings.
Bit 3: Transmit Channel-Data Format (TDATFMT)
Bit 2: Transmit Gapped-Clock Enable (TGPCKEN)
Bit 1: Receive Channel-Data Format (RDATFMT)
Bit 0: Receive Gapped-Clock Enable (RGPCKEN)
BPCS1
0
0
1
1
0 = disable BPCLK pin (pin held at logic 0)
1 = enable BPCLK pin
0 = elastic store is source of multiframe sync
1 = framer or TSYNC pin is source of multiframe sync
0 = interrupts are enabled according to the various mask register settings
1 = interrupts are disabled regardless of the mask register settings
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = TCHCLK functions normally
1 = enable gapped bit-clock output on TCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = RCHCLK functions normally
1 = enable gapped bit-clock output on RCHCLK
TMSS
BPCS0
—
7
0
7
0
0
1
0
1
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
TR.CCR2
Common Control Register 2
71h
TR.CCR3
Common Control Register 3
72h
INTDIS
—
BPCLK Frequency (MHz)
6
0
6
0
16.384
8.192
4.096
2.048
—
—
5
0
5
0
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—-
—
4
0
4
0
TDATFMT
—
3
0
3
0
TGPCKEN
BPCS1
2
0
2
0
RDATFMT
BPCS0
1
0
1
0
RGPCKEN
BPEN
0
0
0
0