DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 93
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10.17.2
FIFO Control
The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3,
4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register
TR.SR6 or TR.SR7 is set. TLWM is a real-time bit and remains set as long as the transmit FIFO’s read pointer is
below the watermark. If enabled, this condition can also cause an interrupt through the INT pin.
When the receive FIFO fills above the high watermark, the RHWM bit in the appropriate HDLC status register is
set. RHWM is a real-time bit and remains set as long as the receive FIFO’s write pointer is above the watermark. If
enabled, this condition can also cause an interrupt through the INT pin.
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