DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 302
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DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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Figure 13-18. G.802 Timing, E1 Mode Only
RCHCLK
TCHCLK
RCHBLK
TCHBLK
NOTES:
1) RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of
Figure 13-19. Transmit Side Timing
NOTES:
1) TSYNC in frame mode (TR.IOCR1.2 = 0).
2) TSYNC in multiframe mode (TR.IOCR1.2 = 1).
3) This diagram assumes both the CAS MF and the CRC-4 MF begin with the TAF frame.
RSYNC
TSYNC
TS #
time slot 26.
FRAME#
TSYNC
TSYNC
TSSYNC
31 32
2
1
0
14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
1
2
3
4
5
6
RCLKO / RSYSCLK
TCLKT / TSYSCLK
RCHCLK / TCHCLK
RCHBLK / TCHBLK
7
RSERO / TSERI
8
9 10
302 of 335
11 12
CHANNEL 25
13 14 15 16 1
LSB MSB
2
3
4
5
CHANNEL 26
6
7
0
8
1 2
9 10
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