DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 273

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
The transmit FDL register (TR.TFDL) contains the FDL information that is to be inserted on a byte basis into the
outgoing T1 data stream. The LSB is transmitted first.
Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code.
Bit 6: Transmit FDL Bit 6 (TFDL6)
Bit 5: Transmit FDL Bit 5 (TFDL5)
Bit 4: Transmit FDL Bit 4 (TFDL4)
Bit 3: Transmit FDL Bit 3 (TFDL3)
Bit 2: Transmit FDL Bit 2 (TFDL2)
Bit 1: Transmit FDL Bit 1 (TFDL1)
Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the transmit FDL code.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL match code.
Bit 6: Receive FDL Match Bit 6 (RFDLM6)
Bit 5: Receive FDL Match Bit 5 (RFDLM5)
Bit 4: Receive FDL Match Bit 4 (RFDLM4)
Bit 3: Receive FDL Match Bit 3 (RFDLM3)
Bit 2: Receive FDL Match Bit 2 (RFDLM2)
Bit 1: Receive FDL Match Bit 1 (RFDLM1)
Bit 0: Receive FDL Match Bit 0 (RFDLM0). LSB of the FDL match code.
Note: Also used to insert Fs framing pattern in D4 framing mode.
RFDLM7
TFDL7
7
0
7
0
RFDLM6
TR.TFDL
Transmit FDL Register
C1h
TR.RFDLM1, TR.RFDLM2
Receive FDL Match Register 1
Receive FDL Match Register 2
C2h, C3h
TFDL6
6
0
6
0
RFDLM5
TFDL5
5
0
5
0
RFDLM4
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TFDL4
4
0
4
0
RFDLM3
TFDL3
3
0
3
0
RFDLM2
TFDL2
2
0
2
0
RFDLM1
TFDL1
1
0
1
0
RFDLM0
TFDL0
0
0
0
0