DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 4

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

11
12
13
10.18 L
10.19 D4/SLC-96 O
10.20 L
10.21 MCLK P
10.22 J
10.23 CMI (C
10.24 R
10.25 T1/E1/J1 T
10.26 P
11.1 C
11.2 P
11.3 F
11.4 T1/E1/J1 T
12.1 R
12.2 T1/E1/J1 T
12.3 G
12.4 A
12.5 S
12.6 E
12.7 T
13.1 MII
13.2 T1 M
10.17.5 Receive Packet-Bytes Available ...........................................................................................................95
10.18.1 Overview ...............................................................................................................................................96
10.18.2 Receive Section ....................................................................................................................................96
10.18.3 Transmit Section ...................................................................................................................................97
10.20.1 LIU Operation........................................................................................................................................98
10.20.2 Receiver ................................................................................................................................................98
10.20.3 Transmitter ..........................................................................................................................................100
10.25.1 BERT Status .......................................................................................................................................107
10.25.2 BERT Mapping....................................................................................................................................107
10.25.3 BERT Repetitive Pattern Set ..............................................................................................................109
10.25.4 BERT Bit Counter................................................................................................................................109
10.25.5 BERT Error Counter............................................................................................................................109
10.25.6 BERT Alternating Word-Count Rate ...................................................................................................109
10.26.1 Number-of-Errors Registers................................................................................................................110
10.26.2 Number of Errors Left Register ...........................................................................................................110
INTERLEAVED PCM BUS OPERATION....................................................................................... 111
DEVICE REGISTERS..................................................................................................................... 118
12.1.1 Global Register Bit Map ......................................................................................................................119
12.1.2 Arbiter Register Bit Map......................................................................................................................120
12.1.3 Serial Interface Register Bit Map ........................................................................................................121
12.1.4 Ethernet Interface Register Bit Map....................................................................................................123
12.1.5 MAC Register Bit Map ........................................................................................................................124
12.4.1 Arbiter Register Bit Descriptions .........................................................................................................143
12.5.1 Serial Interface Transmit and Common Registers..............................................................................144
12.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................144
12.5.3 Transmit HDLC Processor Registers..................................................................................................145
12.5.4 X.86 Registers.....................................................................................................................................151
12.5.5 Receive Serial Interface......................................................................................................................153
12.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................166
12.6.2 MAC Registers ....................................................................................................................................177
12.7.1 Number-of-Errors Left Register...........................................................................................................293
FUNCTIONAL TIMING ................................................................................................................... 294
ITTER
EGACY
INE
RACTIONAL
RANSCEIVER
AYLOAD
ROGRAMMABLE
RBITER
ERIAL
THERNET
ECOMMENDED
HANNEL
EGISTER
LOBAL
AND
I
ODE
NTERFACE
A
ODE
I
NTERFACE
R
RMII I
FDL S
RESCALER
TTENUATOR
R
.................................................................................................................................... 296
E
I
EGISTER
NTERLEAVE
B
EGISTERS
I
RROR
RANSCEIVER
RANSMIT
RANSCEIVER
NTERFACE
M
IT
T1/E1 S
PERATION
ARK
R
M
NTERFACES
UPPORT
EGISTERS
C
APS
U
-I
B
IRCUITS
NIT
I
NSERTION
ACKPLANE
NVERSION
D
R
..................................................................................................................... 101
F
................................................................................................................... 101
................................................................................................................... 119
................................................................................................................... 143
EGISTERS
EFINITIONS FOR
UPPORT
(LIU)........................................................................................................... 98
LOW
M
R
(T1 M
................................................................................................................ 97
BERT F
R
EGISTERS
ODE
........................................................................................................... 102
........................................................................................................... 193
EGISTER
.......................................................................................................... 294
D
IAGRAMS
F
) O
...................................................................................................... 111
C
ODE
..................................................................................................... 113
UNCTION
.................................................................................................... 144
LOCK
PTION
UNCTION
) ............................................................................................... 96
.............................................................................................. 166
B
IT
E
S
......................................................................................... 114
THERNET
........................................................................................ 101
YNTHESIZER
M
(T1 M
AP
................................................................................... 107
4 of 335
................................................................................ 126
ODE
M
APPER
O
..................................................................... 113
NLY
) ........................................................... 110
............................................................ 131