DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 335

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

17 DOCUMENT REVISION HISTORY
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M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
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REVISION
102105
011607
New product release.
Updates for Table 7-1:
(Page 32) Updates for Figure 7-1:
(Page 37, Figure 9-1) Removed reference to 8XCLK. Signal not present in this device.
(Page 39) Corrected low-power mode information in Section 9.2.
(Page 64) Clarified Section 9.16 on X.86 mode synchronization.
(Page 124) Corrected SU.MACCR register map.
(Pages 126 and 200) Changed bits 7, 6, and 5 for TR.T1CCR1 from “—“ to MCLKS, SIE, and
CRC4C; added bit definitions to page 200.
(Pages 127, 234) Corrected/changed definition of TR.LBCR.LIUC (bit 4) to Reserved.
(Page 135) Clarified the GL.C1QPR register definition.
(Page 169) Corrected SU.GCR.H10S bit definition.[
(Page 174) Corrected the SU.RQLT and SU.RQHT default values to zero.
(Page 174) Corrected default value listed in the SU.RMFSRL register definition.
(Page 177) Corrected SU.MACCR.PM and SU.MACCR.PAM bit definitions.
(Page 204) Corrected default value of TR.IDR register.
(Pages 234, 324, 325) Removed references to TDATA (pages 234, 324, 325). Signals not
present in this device.
(Page 244) Added note to TR.CCR2.0 (BPEN) bit description.
(Page 312, Table 14-10) Added TCLKE to TSERO Output Delay Minimum of 3ns; added
TCLKE to TSYNC Setup Time Minimum of 3.5ns.
(Page 327) Added a note regarding the special considerations required for dual JTAG
controllers.
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
(Page 23) Corrected pin description of MDC.
(Page 23) Clarified text regarding use of REF_CLK in DCE and RMII modes.
(Page 23) Corrected pin description of REF_CLKO.
(Page 27) Changed name of RCLKO[1:4] pins to RCLK[1:4] to avoid confusion.
(Page 28) Changed name of RDCLKO[1:4] pins to RCLKO[1:4] to avoid confusion.
(Page 31) Moved ball names for F12, G10, G11, H3, N8, R6 from V
proper JTAG grouping.
Corrected name for ball D15 to V
Corrected name for ball G20 to V
Corrected name for ball H20 to V
Corrected name for ball J20 to V
Corrected name for balls B16–B20, C19, D18, D19, D20, F18, F19, and G16 from V
to V
Changed name for ball L14 from to ZRCLKIO to RCLKI to match pin description.
Changed names for ball F12, G10, G11, H3, N8, R6 from V
grouping.
DD3.3
to match pin description.
© 2007 Maxim Integrated Products
335 of 335
DESCRIPTION
SS
SS
SS
SS
to match pin description.
to match pin description.
to match pin description.
to match pin description.
SS
to DV
SS
SS
to DV
for proper JTAG
SS
for
DD