PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 10

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

3
3.1
3.2
3.2.1
SIGNAL DEFINITIONS
SIGNAL TYPES
SIGNALS
Signal names that end with “#” are active LOW.
PRIMARY BUS INTERFACE SIGNALS
Signal Type
I
O
P
TS
STS
OD
IU
ID
Name
P_AD[31:0]
P_CBE[3:0]#
P_PAR
P_FRAME#
Pin #
J23, M21, M22, L21,
L22, G23, K20, E23,
K21, D23, K22, J21,
J22, H21, H22, G21,
B20, G22, F20, F22,
D18, C19, C17, B17,
A20, C16, B16, A19,
C15, B14, C13, B13
A15, D14, B18, A13
C18
A17
Description
Input Only
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
Open Drain
Internal pull-up on signal
Internal pull-down on signal
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Type
STS
TS
TS
TS
Description
Primary Address / Data: Multiplexed address and data
bus. Address is indicated by P_FRAME# assertion.
Write data is stable and valid when P_IRDY# is asserted
and read data is stable and valid when P_TRDY# is
asserted. Data is transferred on rising clock edges when
both P_IRDY# and P_TRDY# are asserted. During bus
idle, PI7C21P100B drives P_AD[31:0] to a valid logic
level when P_GNT# is asserted.
Primary Command/Byte Enables: Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. After that, the initiator drives the byte enables
during data phases. During bus idle, PI7C21P100B
drives P_CBE[3:0]# to a valid logic level when P_GNT#
is asserted.
Primary Parity. P_PAR is even parity of P_AD[31:0]
and P_CBE[3:0] (i.e. an even number of 1’s). P_PAR is
valid and stable one cycle after the address phase
(indicated by assertion of P_FRAME#) for address
parity. For write data phases, P_PAR is valid one clock
after P_IRDY# is asserted. For read data phase, P_PAR
is valid one clock after P_TRDY# is asserted. Signal
P_PAR is tri-stated one cycle after the P_AD lines are
tri-stated. During bus idle, PI7C21P100B drives P_PAR
to a valid logic level when P_GNT# is asserted.
Primary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME#
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven HIGH for one cycle.
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B