PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 45

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PI7C21P100BEVB

Manufacturer Part Number
PI7C21P100BEVB
Description
MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
Manufacturer
Pericom Semiconductor
Datasheets
1.PI7C21P100BEVB.pdf (77 pages)
2.PI7C21P100BEVB.pdf (79 pages)

Specifications of PI7C21P100BEVB

Lead Free Status / RoHS Status
Not Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not Compliant
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
CACHE LINE SIZE REGISTER – OFFSET 0Ch
PRIMARY LATENCY TIMER – OFFSET 0Ch
HEADER TYPE REGISTER – OFFSET 0Ch
BIST REGISTER – OFFSET 0Ch
BIT
7:0
BIT
31:24
23:16
15:8
BIT
7:0
BIT
15:11
10:8
BIT
23
22:16
BIT
31:24
FUNCTION
Revision ID
FUNCTION
Class Code
Sub Class Code
Programming Interface
FUNCTION
Cache Line Size
FUNCTION
Primary Latency Timer
Primary Latency Timer
FUNCTION
Single Function Device
PCI-to-PCI
Configuration
FUNCTION
BIST
TYPE
TYPE
RO
RO
RO
TYPE
RW
TYPE
RW
RO
TYPE
TYPE
RO
RO
RO
RO
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DESCRIPTION
Specifies the revision of PI7C21P100B. Read as 01h
DESCRIPTION
Specifies the base class code for PI7C21P100B identifying it as a
Bridge device according to PCI specifications. Read as 06h
Specifies the sub-class code identifying PI7C21P100B as a Bridge
device. Read as 04h.
Subtractive decoding not supported. Read as 0h
DESCRIPTION
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions. Not used in PCI-X mode.
bit[7:6]: Not supported and should be 00b
bit[5]: If 1, then cache line size = 32 DWORDS
bit[4]: If 1, then cache line size = 16 DWORDS
bit[3]: If 1, then cache line size = 8 DWORDS
bit[2]: If 1, then cache line size = 4 DWORDS
bit[1:0]: Not supported and should be 00b
DESCRIPTION
Designates the upper 5 bits of the primary latency timer in PCI clock
units
Designates the lower 3 bits of the primary latency timer in PCI clock
units. Returns 000 when read to force 8-cycle increments for the
latency timer.
DESCRIPTION
Returns 0 when read to designate single function device
Returns 0000001 when read.
DESCRIPTION
BIST not supported. Returns 0 when read.
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B