PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 61
PI7C21P100BEVB
Manufacturer Part Number
PI7C21P100BEVB
Description
MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
Manufacturer
Pericom Semiconductor
Specifications of PI7C21P100BEVB
Lead Free Status / RoHS Status
Not Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not Compliant
8.1.55
PCI-X BRIDGE PRIMARY STATUS REGISTER – OFFSET 84h
BIT
19
18
17
16
BIT
31:22
21
20
19
18
17
16
15:8
FUNCTION
Unexpected Split
Completion
Split Completion
Discarded
133MHz Capable
64-bit Device
FUNCTION
RESERVED
Split Request Delayed
Split Completion
Overrun
Unexpected Split
Completion
Split Completion
Discarded
133MHz Capable
64-bit Device
Bus Number
TYPE
TYPE
RO
RW
RO
RW
RW
RO
RO
RW
RW
RW
RO
RO
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DESCRIPTION
Unexpected Split Completion
0: No unexpected split completion has been received.
1: An unexpected split completion has been received with the
requested ID equal to the bridge’s secondary bus number, device
number 00h, and function number 0 on the bridge secondary
interface.
Reset to 0
Split Completion Discarded
0: No split completion has been discarded.
1: A split completion moving toward the secondary bus has been
discarded by the bridge because the requester would not accept it.
Reset to 0.
133MHz Capable
Returns 1 when read to indicate PI7C21P100B is capable of 133MHz
operation on the secondary interface.
64-bit Device
Returns a 1 when the AD interface is 64-bits wide on the secondary
bus and 64BIT_DEV#=1. Returns a 0 when 64BIT_DEV#=0.
DESCRIPTION
Reserved. Returns 00000000 when read.
Split Request Delayed
0: PI7C21P100B has not delayed a split request.
1: A split request moving toward the primary bus has been delayed
by PI7C21P100B because there is not enough room within the limit
specified in the split transaction commitment limit field in the
upstream split transaction control register.
Reset to 0
Split Completion Overrun
0: PI7C21P100B has accepted all split completions.
1: PI7C21P100B has terminated a split completion on the primary
bus with retry or disconnect at the next ADB because the buffers in
the bridge were full.
Reset to 0
Unexpected Split Completion
0: No unexpected split completion has been received.
1: An unexpected split completion has been received with the
requested ID equal to the bridge’s primary bus number, device
number, and function number on the bridge pirmary interface.
Reset to 0
Split Completion Discarded
0: No split completion has been discarded.
1: A split completion moving toward the primary bus has been
discarded by the bridge because the requester would not accept it.
Reset to 0.
133MHz Capable
Returns 1 when read to indicate PI7C21P100B is capable of 133MHz
operation on the primary interface.
64-bit Device
Returns a 1 when the AD interface is 64-bits wide on the primary bus
and P_REQ64#=0 at P_RST# de-assertion. Otherwise, AD interface
is 32-bits wide.
Bus Number
This is an additional address from which the contents of the primary
bus number register on type 1 configuration space header is read. The
bridge uses the bus number, device number, and function number
fields to create the completer ID when responding with a split
completion to a read of an internal bridge register. These fields are
also used for cases when one interface is in conventional PCI mode
and the other is in PCI-X mode.
Reset to 11111111
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B