PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 38

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

7
7.1
7.2
Table 6-2 DRIVER IMPEDANCE SELECTION
RESET
The primary and secondary interface each have their own asynchronous reset signal used at
power-on and at other times to put PI7C21P100B into a known state. The reset signal on the
primary (P_RST#) is an input pin, while the reset signal on the secondary (S_RST#) is an
output pin driven by PI7C21P100B.
PRIMARY INTERFACE RESET
When P_RST# is asserted, the following events occur:
PI7C21P100B is not accessible during P_RST#. After P_RST# is deasserted in PCI-X mode,
PI7C21P100B remains inaccessible for 100us to enable the internal PLL to lock to its target
frequency. In conventional PCI mode, PI7C21P100B is held in reset 7 PCI clocks after the
deassertion of P_RST#.
SECONDARY INTERFACE RESET
PI7C21P100B is responsible for driving the secondary bus reset signals, S_RST#. PI721P100
asserts S_RST# when any of the following conditions are met:
Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# is asserted
and does not de-assert until P_RST# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RST# remains
asserted until a configuration write operation clears the secondary reset bit.
Several things must occur at or prior to the de-assertion of S_RST#. Once P_RST# is
de-asserted or the secondary bus reset bit is changed from 1 to 0, PI7C21P100B will wait for
the S_CLK_STABLE signal to be asserted before proceeding. S_CLK must be stable at a
frequency within the bus capability limits prior to the assertion of S_CLK_STABLE. Since
the PCI Local Bus Specification requires that the bus clock be stable for at least 100us prior to
the de-assertion of the bus reset, S_CLK_STABLE serves as a gate to a timer that ensures that
Primary Bus
Mode
Conventional
PCI
PCI-X 66
PCI-X 100
PCI-X 133
PI7C21P100B immediately tri-states all primary PCI interface signals. S_AD[31:0] and
S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri-
stated.
PI7C21P100B performs a chip reset.
Registers that have default values are reset.
Default Driver
Mode
(P_DRVR=0)
20 ohm
20 ohm
20 ohm
20 ohm
Driver Mode if
(P_DRVR=1)
Page 38 of 79
40 ohm
40 ohm
40 ohm
20 ohm
Secondary Bus
Mode
Conventional
PCI
PCI-X 66
PCI-X 100
PCI-X 133
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
Default Driver
Mode
(S_DRVR=0)
20 ohm
20 ohm
20 ohm
40 ohm
PI7C21P100B
Driver Mode if
(S_DRVR=1)
40 ohm
40 ohm
40 ohm
20 ohm