PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 53

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

8.1.36
8.1.37
MISCELLANEOUS CONTROL REGISTER – OFFSET 44h
EXTENDED CHIP CONTROL REGISTER 1 – OFFSET 48h
BIT
7:3
2
1
0
BIT
7
6
5
4
FUNCTION
RESERVED
Primary Configuration
Busy
Data Parity Error
Recovery Enable
Parity Error Behavior
FUNCTION
RESERVED
Bridge Disconnect
Discard Timer
Memory Write
Transaction Entry
Control
Synchronous Mode
Enable
TYPE
TYPE
RO
RW
RW
RW
RO
RW
RW
RW
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DESCRIPTION
Reserved. Returns 00000 when read.
Primary Configuration Busy
0: Type 0 configuration commands accepted normally on the primary
interface.
1: Type 0 configuration commands retried on the primary interface.
This bit can be read from both the primary and secondary buses, but
written only from the secondary bus.
Reset value is based on P_CFG_BUSY strapping. If P_CFG_BUSY
is tied HIGH, reset to 1.
Data Parity Error Recovery Enable
0: All PI7C21P100B to pass parity errors through.
1: Cause SERR# to be asserted whenever either master-data-parity-
error bit[8] is set.
Reset to 1.
Parity Error Behavior
0: PI7C21P100B will pass the corrupted data sequence and PERR#
will be asserted (if enabled), but PI7C21P100B will not complete the
data and CBE# for performing completion on the initiating bus when
detecting a data parity error on a non-posted write transaction.
1: Transaction will be completed on the originating bus, PERR# will
be asserted (if enabled), he appropriate status bits will be set, the data
will be discarded and no request will be queued.
Reset to 1.
DESCRIPTION
Reserved. Returns 0 when read.
Bridge Disconnect Discard Control
0: PI7C21P100B will discard remaining data after it disconnects the
external master during burst memory reads transaction on the PCI
source bus.
1: PI7C21P100B will keep remaining data after it disconnects the
external master during burst memory reads on the PCI source bus,
until the external master returns or the discard timer expires.
Reset to 0.
Memory Write Transaction Entry Control
0: PI7C21P100B can accept 4 memory write transactions
1: PI7C21P100B can accept 8 memory write transactions
Reset to 0.
Synchronous Mode Enable
0: Synchronous mode is disabled, and the asynchronous clock input
is supported.
1: Synchronous mode is enabled and is used to decrease the
frequency to frequency latency when PI7C21P100B is forwarding
transactions through the bridge. The clock inputs have to be
synchronized and the primary clock need to lead the secondary clock
with the following combinations:
Reset to 0
133MHz
133MHz
Primary
33MHz
66MHz
66MHz
Secondary
33MHz
66MHz
33MHz
133MHz
66MHz
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
0 – 14ns
0 – 7ns
3 – 14ns
0 – 3ns
3 – 7ns
time
PI7C21P100B