PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 7

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

9
10
11
12
9.1
9.2
9.3
9.4
9.5
10.1
10.2
10.3
10.4
8.1.32
8.1.33
8.1.34
8.1.35
8.1.36
8.1.37
8.1.38
8.1.39
8.1.40
8.1.41
8.1.42
8.1.43
8.1.44
8.1.45
8.1.46
8.1.47
8.1.48
8.1.49
8.1.50
8.1.51
8.1.52
8.1.53
8.1.54
8.1.55
8.1.56
8.1.57
8.1.58
8.1.59
8.1.60
8.1.61
8.1.62
8.1.63
8.1.64
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .................................................................. 66
ELECTRICAL INFORMATION.................................................................................................... 75
MECHANICAL INFORMATION.................................................................................................. 78
ORDERING INFORMATION........................................................................................................ 78
INSTRUCTION REGISTER .................................................................................................... 66
BYPASS REGISTER................................................................................................................ 66
DEVICE ID REGISTER ........................................................................................................... 66
BOUNDARY SCAN REGISTER............................................................................................. 67
JTAG BOUNDARY REGISTER ORDER ............................................................................... 67
MAXIMUM RATINGS ............................................................................................................ 75
DC SPECIFICATIONS............................................................................................................. 75
AC SPECIFICATIONS............................................................................................................. 76
POWER CONSUMPTION ....................................................................................................... 77
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................ 49
BRIDGE CONTROL REGISTER – OFFSET 3Ch ........................................................... 50
PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h........................ 51
SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h.................. 52
MISCELLANEOUS CONTROL REGISTER – OFFSET 44h........................................... 53
EXTENDED CHIP CONTROL REGISTER 1 – OFFSET 48h......................................... 53
EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h......................................... 54
ARBITER MODE REGISTER – OFFSET 50h................................................................. 54
ARBITER ENABLE REGISTER – OFFSET 54h.............................................................. 55
ARBITER PRIORITY REGISTER – OFFSET 58h ........................................................... 55
SERR# DISABLE REGISTER – OFFSET 5Ch ................................................................ 56
PRIMARY RETRY COUNTER REGISTER – OFFSET 60h............................................. 57
SECONDARY RETRY COUNTER REGISTER – OFFSET 64h....................................... 57
DISCARD TIMER CONTROL REGISTER – OFFSET 68h............................................. 58
RETRY AND TIMER STATUS REGISTER – OFFSET 6Ch ............................................ 58
OPAQUE MEMORY ENABLE REGISTER – OFFSET 70h ............................................ 59
OPAQUE MEMORY BASE REGISTER – OFFSET 74h ................................................. 59
OPAQUE MEMORY LIMIT REGISTER – OFFSET 74h ................................................ 59
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER – OFFSET 78h ....................... 59
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER – OFFSET 7Ch...................... 60
PCI-X CAPABILITY ID REGISTER – OFFSET 80h ....................................................... 60
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ........................................... 60
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h............................................. 60
PCI-X BRIDGE PRIMARY STATUS REGISTER – OFFSET 84h ................................... 61
SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ... 62
PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch .. 62
POWER MANAGEMENT ID REGISTER – OFFSET 90h............................................... 63
NEXT CAPABILITIES POINTER REGISTER – OFFSET 90h........................................ 63
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 90h.......................... 63
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h ......... 63
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h ................. 64
SECONDARY BUS PRIVATE DEVICE MASK REGISTER – OFFSET B0h................... 64
MISCELLANEOUS CONTROL REGISTER 2 – OFFSET B8h ....................................... 65
Page 7 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B