PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 48

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PI7C21P100BEVB

Manufacturer Part Number
PI7C21P100BEVB
Description
MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
Manufacturer
Pericom Semiconductor
Datasheets
1.PI7C21P100BEVB.pdf (77 pages)
2.PI7C21P100BEVB.pdf (79 pages)

Specifications of PI7C21P100BEVB

Lead Free Status / RoHS Status
Not Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not Compliant
8.1.21
8.1.22
8.1.23
8.1.24
8.1.25
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h
BIT
22
21
20:16
BIT
15:4
3:0
BIT
31:20
19:16
BIT
15:4
3:0
BIT
31:20
19:16
BIT
31:0
FUNCTION
Reserved
66MHz Capable
Reserved
FUNCTION
Memory Base
Reserved
FUNCTION
Memory Limit
Reserved
FUNCTION
Prefetchable Memory
Base
64-bit Addressing
FUNCTION
Prefetchable Memory
Limit
64-bit Addressing
FUNCTION
Prefetchable Base
Upper 32-bit
TYPE
TYPE
RW
RO
TYPE
RW
RO
TYPE
RO
TYPE
RO
TYPE
RO
RO
RO
RW
RW
RW
Page 48 of 79
DESCRIPTION
Reserved. Returns 0 when read.
66MHz Capable Status
1: Capable of 66MHz operation
Returns 1 when read.
Reserved. Returns 00000 when read.
DESCRIPTION
Specifies the base of the memory mapped I/O address range
bit[31:20] and is used with the Memory Limit register to specify a
range of 32-bit addresses supported for memory mapped I/O
transactions.
Reset to 800h
Reserved. Returns 0 when read
DESCRIPTION
Specifies address bits[31:20] of the limit address for the address
range of memory mapped I/O operations.
Reset to 000h
Reserved. Returns 0 when read
DESCRIPTION
Specifies address bits[31:20] of the base address for the address
range of prefetchable memory operations.
Reset to 800h
Designates 64-bit addressing support. Returns 1h when read.
DESCRIPTION
Specifies address bits[31:20] of the limit address for the address
range of prefetchable memory operations.
Reset to 800h
Designates 64-bit addressing support. Returns 1h when read.
DESCRIPTION
Specifies address bits[63:32] of the base address for the address
range of prefetchable memory operations.
Reset to 0000 0000h
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B