PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 17

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

3.2.7
JTAG BOUNDARY SCAN AND TEST SIGNALS
64BIT_DEV#
BAR_EN
IDSEL_ROUTE
OPAQUE_EN
P_CFG_BUSY
RESERVED
Name
TCK
TMS
TDO
TDI
Y22
G2
AC22
AA18
C6
D1
Pin #
F21
D22
B23
C22
Page 17 of 79
Type
IU
IU
IU
O
I
I
I
I
-
I
PCI-X Device Bus Width: 64BIT_DEV# sets bit 16 of
the PCI-X Bridge Status Register to support system
management software. This signal does not change the
behavior of the bridge.
0: Sets bit 16 of the PCI-X bridge status register to 1
1: Sets bit 16 of the PCI-X bridge status register to 0
Base Address Register Enable: BAR_EN is used to
enable the base address at reset or power up. When
enabled, the 64-bit register at offset 10h and offset 14h is
used to claim a 1MB memory region.
0: Disabled – register returns 0 and no memory region is
claimed
1: Enabled – bits 63:20 can be written by software to
claim a 1MB memory region
IDSEL Reroute Enable: Controls the IDSEL reroute
function at reset or power up. The reset value of the
secondary bus private device mask register is changed
according to the value of this pin.
0: Reset value of the secondary bus private device mask
register is 00000000h
1: Reset value of the secondary bus private device mask
register is 22F20000h
Opaque Region Enable: Used to enable the opaque
memory region at reset or power up. Controls bit[0]
offset 70h.
0: Disable opaque memory address range
1: Enable opaque memory address range
Primary Configuration Busy: Determines the initial
value of bit [2] offset 44h to sequence initialization on
the primary and secondary buses for applications that
require bridge configuration from the secondary bus.
Applications that do not require retry configuration
transactions from the primary bus should pull this pin
down to LOW. P_CFG_BUSY only controls the
configuration access on the primary bus. The secondary
configuration access is independent of this pin.
0: Type 0 configuration commands accepted normally on
the primary bus.
1: Type 0 configuration commands are retried on the
primary bus.
Reserved. Must be tied to ground.
Description
Test Clock. Used to clock state information and data
into and out of the PI721P100 during boundary scan.
Test Mode Select. Used to control the state of the Test
Access Port controller.
Test Data Output. Used as the serial output for the test
instructions and data from the test logic.
Test Data Input. Serial input for the JTAG instructions
and test data.
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B