PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 44
PI7C21P100BEVB
Manufacturer Part Number
PI7C21P100BEVB
Description
MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
Manufacturer
Pericom Semiconductor
Specifications of PI7C21P100BEVB
Lead Free Status / RoHS Status
Not Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not Compliant
8.1.5
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
2
1
0
BIT
31
30
29
28
27
26:25
24
23
22
21
20
19:16
FUNCTION
Bus Master Enable
Memory Space Enable
I/O Space Enable
FUNCTION
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
DEVSEL# Timing
Data Parity Error
Fast Back-to-Back
Capable
Reserved
66MHz Capable
Capability List
Reserved
TYPE
RW
RW
TYPE
RO
RO
RW
RWC
RWC
RWC
RWC
RWC
RWC
RO
RO
RO
RO
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DESCRIPTION
Bus Master Control
0: PI7C21P100B does not initiate memory and I/O transactions on
the primary and disables responses to memory and I/O transactions
on the secondary
1: Enables PI7C21P100B to operate as a master on the primary for
memory and I/O transactions forwarded from the secondary.
In PCI-X mode, PI7C21P100B is allowed to initiate a split
completion transaction regardless of the status of this bit. Reset to 0
Memory Space Control
0: Ignore memory transactions on the primary
1: Enables responses to memory transactions on the primary
Reset to 0
I/O Space Control
0: Ignores I/O transactions on the primary
1: Enables responses to I/O transaction on the primary
Reset to 0
DESCRIPTION
Detected Parity Error Status
0: Address or data parity error not detected by PI7C21P100B
1: Address or data parity error detected by PI7C21P100B
Reset to 0
Signaled System Error Status
0: PI7C21P100B did not assert SERR#
1: PI7C21P100B asserted SERR#
Reset to 0
Received Master Abort Status
0: Transaction not terminated with a bus master abort
1: Transaction terminated with a bus master abort
Reset to 0
Received Target Abort Status
0: Transaction not terminated with a target abort
1: Transaction terminated with a target abort
Reset to 0
Signaled Target Abort Status
0: Target device did not terminate transaction with a target abort
1: Target device terminated transaction with a target abort
DEVESEL# Timing Status
01: Medium decoding.
Returns 01h when read.
Data Parity Error Status
0: No data parity error detected
1: Data parity error detected
Reset to 0
Fast Back-to-Back Status
0: Target not capable of decoding fast back-to-back transactions in
PCI-X mode
1: Target capable of decoding fast back-to-back transactions in
conventional PCI mode
Returns 0 in PCI-X mode and 1 in conventional PCI mode
Reserved. Returns 0 when read.
66MHz Capable Status
1: Capable of 66MHz operation
Returns 1 when read.
Capability List
1: PI7C21P100B supports the capability list and offset 34h is the
pointer to the data structure.
Returns 0 when read.
Reserved. Returns 0000 when read.
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B