PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 6

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

6
7
8
5.2
6.1
6.2
6.3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8.1
CLOCKS............................................................................................................................................ 35
6.3.1
6.3.2
6.3.3
6.3.4
RESET ............................................................................................................................................... 38
CONFIGURATION REGISTERS .................................................................................................. 42
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
8.1.12
8.1.13
8.1.14
8.1.15
8.1.16
8.1.17
8.1.18
8.1.19
8.1.20
8.1.21
8.1.22
8.1.23
8.1.24
8.1.25
8.1.26
8.1.27
8.1.28
8.1.29
8.1.30
8.1.31
ORDERING RULES................................................................................................................. 33
PRIMARY AND SECONDARY CLOCK INPUTS................................................................. 35
CLOCK JITTER........................................................................................................................ 35
MODE AND CLOCK FREQUENCY DETERMINATION .................................................... 36
PRIMARY INTERFACE RESET............................................................................................. 38
SECONDARY INTERFACE RESET....................................................................................... 38
BUS PARKING & BUS WIDTH DETERMINATION............................................................ 40
SECONDARY DEVICE MASKING ....................................................................................... 40
ADDRESS PARITY ERRORS ................................................................................................. 40
OPTIONAL BASE ADDRESS REGISTER............................................................................. 40
OPTIONAL CONFIGURATION ACCESS FROM THE SECONDARY BUS ...................... 41
SHORT TERM CACHING....................................................................................................... 41
CONFIGURATION REGISTER SPACE MAP ....................................................................... 42
PRIMARY BUS ..................................................................................................................... 36
SECONDARY BUS ............................................................................................................... 36
CLOCK STABILITY.............................................................................................................. 37
DRIVER IMPEDANCE SELECTION................................................................................... 37
SIGNAL TYPE DEFINITION ............................................................................................... 43
VENDOR ID REGISTER – OFFSET 00h............................................................................. 43
DEVICE ID REGISTER – OFFSET 00h .............................................................................. 43
COMMAND REGISTER – OFFSET 04h.............................................................................. 43
PRIMARY STATUS REGISTER – OFFSET 04h .................................................................. 44
REVISION ID REGISTER – OFFSET 08h ........................................................................... 45
CLASS CODE REGISTER – OFFSET 08h........................................................................... 45
CACHE LINE SIZE REGISTER – OFFSET 0Ch ................................................................. 45
PRIMARY LATENCY TIMER – OFFSET 0Ch ..................................................................... 45
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 45
BIST REGISTER – OFFSET 0Ch .................................................................................... 45
LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h .................................. 46
UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h................................... 46
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ................................................... 46
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ............................................. 46
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ......................................... 46
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................ 46
I/O BASE ADDRESS REGISTER – OFFSET 1Ch........................................................... 47
I/O LIMIT REGISTER – OFFSET 1Ch............................................................................ 47
SECONDARY STATUS REGISTER – OFFSET 1Ch ....................................................... 47
MEMORY BASE REGISTER – OFFSET 20h .................................................................. 48
MEMORY LIMIT REGISTER – OFFSET 20h ................................................................. 48
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h.................................... 48
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h................................... 48
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h............................ 48
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch.......................... 49
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h.................................................... 49
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h .................................................. 49
CAPABILITY POINTER – OFFSET 34h ......................................................................... 49
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h .................................. 49
INTERRUPT LINE REGISTER – OFFSET 3Ch.............................................................. 49
Page 6 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B