PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 24

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

4.2.1.1
4.2.1.2
4.2.1.3
queue empties. PI7C21P100B will restart the follow-on transactions if the queue has new
data.
PI7C21P100B ends the transaction on the target bus when one of the following conditions is
met:
When both buses are operating in the PCI-X mode, PI7C21P100B passes the memory write
command that it receives to the destination interface along with the originating byte count and
transaction ID. PI7C21P100B attempts to transfer a memory write command when the
transaction ends or a 128-byte boundary is crossed. As long as there is at least 128-byte of
data in the data buffer or the end of transfer remains from the PCI-X memory write command
when a 128-byte boundary is crossed, the transfer will continue. If a transaction is
disconnected on the destination interface in the middle of a continuing transfer, the byte count
and address are updated and the transaction is presented again on the destination interface. If a
transaction is disconnected in the middle of a continuing transfer on the originating interface,
the originator must present the transaction again with the updated byte count and address.
When both buses are operating in conventional PCI mode, the bridge passes the memory write
command that it receives to the destination interface, unless PI7C21P100B is disconnected in
the middle of a memory write and invalidate and is not on a cache line boundary. If this
happens, the command will continue as a memory write when PI7C21P100B attempts to
reconnect. PI7C21P100B attempts to transfer a memory write command when the transaction
ends or a 128-byte boundary is crossed. As long as a 128-byte buffer is full or the end of
transfer remains from the memory write command when a 128-byte boundary is crossed, the
transfer will continue.
When the originating bus is operating in the conventional PCI mode and the destination bus is
operating in the PCI-X mode, PI7C21P100B must buffer memory write transactions from the
conventional PCI interface and count the number of bytes to be forwarded to the PCI-X
interface. If the conventional PCI transaction uses the memory write command and some byte
enables are not asserted, PI7C21P100B must use the PCI-X memory write command. If the
conventional PCI command is memory write and all byte enables are asserted, PI7C21P100B
will use the PCI-X memory write command. If the conventional transaction uses the memory
write and invalidate command, PI7C21P100B uses the PCI-X memory write block command.
PCI-X TO PCI-X
PCI TO PCI
PCI TO PCI-X
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C21P100B starts another
transaction to deliver the rest of the write data).
The target returns a target abort (PI7C21P100B discards remaining write data).
The master latency timer expires, and PI7C21P100B no longer has the target bus grant
(PI7C21P100B starts another transaction to deliver remaining write data).
Page 24 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B