PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 30

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

4.4.1
4.4.2
To support hierarchical PCI bus systems, two types of configuration transactions are
specified: Type 0 and Type 1.
Type 0 configuration transactions are issued when the intended target resides on the same PCI
bus as the initiator. A Type 0 configuration transaction is identified by the configuration
command and the lowest two bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI
bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration
command is identified by the configuration command and
the lowest two address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWORD
address of the configuration register to be accessed. The function number is also included in
both Type 0 and Type 1 formats and indicates which function of a multifunction device is to
be accessed. For single-function devices, this value is not decoded. The addresses of Type 1
configuration transaction include a 5-bit field designating the device number that identifies
the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1
transactions specifies the PCI bus to which the transaction is targeted.
TYPE 0 ACCESS TO PI7C21P100B
The configuration space is accessed by a Type 0 configuration transaction. The configuration
space can be accessed from the primary or secondary interface. S_IDSEL should be tied LOW
if access is not required from the secondary interface.
On the primary interface, PI7C21P100B responds to a Type 0 configuration transaction by
accepting the transaction when the following conditions are met during the address phase:
On the secondary interface, PI7C21P100B responds to a Type 0 configuration transaction by
accepting the transaction when the following conditions are met during the address phase:
The function number is not decoded since the bridge is a single-function device. All
configuration transactions to the bridge are handled as DWORD operations.
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a
hierarchical PCI/PCI-X bus system. A bridge is the only type of device that should respond to
a Type 1 configuration command. Type 1 configuration commands are used when the
configuration access is intended for a PCI/PCI-X device that resides on a bus other than the
one where the Type 1 transaction is generated.
P_CBE[3:0]# indicates a configuration write or configuration read transaction
The two lowest address bits on P_AD[1:0] are 00
P_IDSEL is asserted
Bit[2] offset 44h (Miscellaneous Control Register) is 0
S_CBE[3:0]# indicates a configuration write or configuration read transaction
The two lowest address bits on S_AD[1:0] are 00
S_IDSEL is asserted
Page 30 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B