PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 11

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

Name
P_IRDY#
P_TRDY#
P_DEVSEL#
P_STOP#
P_LOCK#
P_IDSEL
P_PERR#
P_SERR#
P_REQ#
P_GNT#
P_RST#
Pin #
A16
B15
D21
C4
C14
B19
C8
B4
B21
C20
E22
Page 11 of 79
Type
STS
STS
STS
STS
STS
OD
TS
I
I
I
I
Description
Primary IRDY (Active LOW). Driven by the initiator
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven HIGH for one cycle.
Primary TRDY (Active LOW). Driven by the target of
a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven HIGH for one cycle.
Primary Device Select (Active LOW). Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C21P100B waits for the
assertion of this signal within 5 cycles of P_FRAME#
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven HIGH for one cycle.
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to stop
the current transaction. Before tri-stated, it is driven
HIGH for one cycle.
Primary LOCK (Active LOW). Asserted by an
initiator, one clock cycle after the first address phase of a
transaction, attempting to perform an operation that may
take more than one PCI transaction to complete.
Primary ID Select. Used as a chip select line for Type
0 configuration access to PI721P100 configuration
space.
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven
HIGH for one cycle.
Primary System Error (Active LOW). Can be driven
LOW by any device to indicate a system error condition.
PI7C21P100B drives this pin on:
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW): This is asserted by
PI7C21P100B to indicate that it wants to start a
transaction on the primary bus. PI7C21P100B de-asserts
this pin for at least 2 PCI clock cycles before asserting it
again.
Primary Grant (Active LOW): When asserted,
PI7C21P100B can access the primary bus. During idle
and P_GNT# asserted, PI7C21P100B will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW): When P_RESET# is
active, all PCI signals should be asynchronously tri-
stated.
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B