PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 40

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

7.3
7.4
7.5
7.6
BUS PARKING & BUS WIDTH DETERMINATION
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while
the bus is idle. In general, the device implementing the bus arbiter is responsible for parking
the bus or assigning another device to park the bus. A device parks the bus when the bus is
idle, its bus grant is asserted, and the device’s request is not asserted. The AD[31:0],
CBE[3:0], and PAR signals are driven LOW after assertion of S_RST#.
PI7C21P100B will assert S_REQ64# for at least 10 PCI clock cycles to allow devices to
determine whether they are connected on a 64-bit bus or 32-bit bus.
SECONDARY DEVICE MASKING
Secondary devices can be masked through configuration or power strapping of the secondary
bus private device mask register. The process of converting Type 1 configuration transactions
to Type 0 configuration transactions is modified by the contents of the secondary bus private
device mask register. A configuration transaction that targets a device masked by this register
is routed to device 15. Secondary bus architectures which are designed to support masking of
devices should not implement a device number 15 (i.e., S_AD(31)). The device mask bit
options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by PI7C21P100B allow architectures
to support private device groupings that use a single or multiple interrupt binding.
ADDRESS PARITY ERRORS
PI7C21P100B checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C21P100B detects an address parity error, the transaction will not
be claimed and will be allowed to terminate with a master abort. The result of an address
parity error will be controlled by the parity error response bits in both the command and
bridge control registers.
OPTIONAL BASE ADDRESS REGISTER
The 64 bit Base Address register located in the configuration register at offsets 10h and 14h
can optionally be used to acquire a 1 MB memory region at system initialization.
PI7C21P100B uses this register to claim an additional prefetchable memory region for the
secondary bus. When used with the secondary device masking, this allows for the acquisition
of memory space for private devices that are not otherwise viewable by the system software.
This 64 bit base address register and the memory space defined by it are enabled by the
BAR_EN. When BAR_EN is pulled LOW, this register location returns zeros for reads and
cannot be written. When BAR_EN is pulled HIGH, the upper memory base address register
and lower memory base address registers combined specify address bits 63:20 of a memory
region. Memory accesses on the primary bus are compared against this register, if address bits
63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory
base address register and the upper memory base address register, the access is claimed by
PI7C21P100B and passed through to the secondary bus. Memory accesses on the secondary
bus are also compared against this register, if address bits 63:20 are equal to bits 63:20 of the
address defined by the combination of the lower memory base address register and the upper
memory base address register, the access is ignored by the bridge.
Page 40 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B