PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 42
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PI7C21P100BEVB
Manufacturer Part Number
PI7C21P100BEVB
Description
MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
Manufacturer
Pericom Semiconductor
Specifications of PI7C21P100BEVB
Lead Free Status / RoHS Status
Not Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not Compliant
8
8.1
Table 8-1 CONFIGURATION SPACE MAP
CONFIGURATION REGISTERS
PCI configuration defines a 64 DWORD space to define various attributes of PI7C21P100B.
CONFIGURATION REGISTER SPACE MAP
Secondary Latency
PCI-to-PCI Bridge Support Extension
31 – 24
Secondary Data Buffering Control
Timer
BIST
Power Management Capabilities
Prefetchable Memory Limit
PCI-X Secondary Status
Opaque Memory Limit
I/O Limit Upper 16-bit
Secondary Status
Primary Status
Memory Limit
Bridge Control
Device ID
Reserverd
Reserved
Reserved
Subordinate Bus
Primary Bus Downstream Split Transaction
Secondary Bus Upstream Split Transaction
Header Type
Class Code
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Opaque Memory Limit Upper 32-bit
Secondary Bus Private Device Mask
Opaque Memory Base Upper 32-bit
Number
23 – 16
Prefetchable Limit Upper 32-bit
Prefetchable Base Upper 32-bit
Expansion ROM Base Address
Lower Memory Base Address
Upper Memory Base Address
Secondary Retry Counter
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Primary Retry Counter
PCI-X Bridge Status
Bit Number
Reserved
Reserved
Reserved
Reserved
Secondary Bus Number
Next Capability Pointer
Primary Latency Timer
Extended Chip Control
Next Capabilities
Interrupt Pin
Power Management Control and Status
I/O Limit
Pointer
15 – 8
Primary Data Buffering Control
2
Prefetchable Memory Base
2-PORT PCI-X TO PCI-X BRIDGE
Miscellaneous Control 2
I/O Base Upper 16-bit
Opaque Memory Base
Primary Command
Memory Base
Arbiter Mode
Vendor ID
November 2005 – Revision 1.02
Retry and Timer Status
Power Management ID
Extended Chip Control
Miscellaneous Control
Discard Timer Control
Primary Bus Number
PCI-X Capability ID
Capability Pointer
Opaque Memory
Cache Line Size
SERR# Disable
Arbiter Priority
Arbiter Enable
Interrupt Line
Revision ID
I/O Base
Enable
7 - 0
1
PI7C21P100B
DWORD
Address
BCh-FFh
98h-Ach
0Ch
1Ch
2Ch
3Ch
4Ch
5Ch
6Ch
7Ch
8Ch
B0h
B4h
B8h
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
50h
54h
58h
60h
64h
68h
70h
74h
78h
80h
84h
88h
90h
94h