PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 62

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

8.1.56
8.1.57
SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER –
OFFSET 88h
PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER
– OFFSET 8Ch
BIT
7:3
2:0
BIT
31:16
15:0
BIT
31:16
FUNCTION
Device Number
Function Number
FUNCTION
Split Transaction
Commitment Limit
Split Transaction
Capability
FUNCTION
Split Transaction
Commitment Limit
TYPE
RO
TYPE
TYPE
RO
RW
RO
RW
Page 62 of 79
DESCRIPTION
Device Number
The device number (AD[15:11]) of a type 0 configuration transaction
is assigned to the bridge by the connection of system hardware. Each
time the bridge is addressed by a configuration write transaction, the
bridge updates this register with the contents of AD[15:11] of the
address phase of the configuration transaction, regardless of which
register in the bridge is addressed by the transaction. The bridge is
addressed by a configuration write transaction if all of the following
are true:
- The transaction uses a configuration write command
- IDSEL is asserted during the address phase
- AD[1:0] are 00 (type 0 configuration transaction)
- AD[10:8] of the configuration address contain the appropriate
function number
Reset to 11111
Function Number
The function number (AD[10:8]) of the address of a type 0
configuration transaction to which the bridge responds.
Reset to 000
DESCRIPTION
Split Transaction Commitment Limit
This field indicates the cumulative sequence size of the commitment
limit in units of ADQ’s. Software is allowed to program this field to
any value greater than or equal to the contents of the split transaction
capacity field. For example, if the limit is set to FFFFh, the bridge is
allowed to forward all split requests of any size regardless of the
amount of buffer space available. If the limit is set to 0100h or
greater, causes the bridge to forward accepted split requests of any
size regardless of the amount of buffer space available. The limit can
be programmed at any time after reset. The value of the limit is equal
to the split transaction capacity field reset.
Reset to 0020h
Split Transaction Capability
The bridge returns 0020h to indicate that there are 32 ADQ’s (4K
bytes) available buffer space for storing split completions for
memory reads. This applies to requesters on the secondary bus
addressing completers on the primary bus.
Reset to 0020h
DESCRIPTION
Split Transaction Commitment Limit
This field indicates the cumulative sequence size of the commitment
limit in units of ADQ’s. Software is allowed to program this field to
any value greater than or equal to the contents of the split transaction
capacity field. For example, if the limit is set to FFFFh, the bridge is
allowed to forward all split requests of any size regardless of the
amount of buffer space available. If the limit is set to 0100h or
greater, the bridge will forward accepted split requests of any size
regardless of the amount of buffer space available. The limit can be
programmed at any time after reset. The value of the limit is equal to
the split transaction capacity field reset.
Reset to 0020h
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B