82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 16

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
PIN DESCRIPTION
IDT82V2042E
MONT2
MONT1
GNDIO
VDDIO
Name
TRST
TMS
TDO
RST
THZ
TCK
JA1
JA0
TDI
Pullup
Pullup
Pullup
Type
O
-
-
I
I
I
I
I
I
I
I
I
I
Pin No.
7,40
8,39
16
17
18
19
21
20
1
2
3
4
5
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only used
in hardware control mode)
•
•
•
•
In software control mode, this pin should be connected to ground.
See above.
MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns. MCLK must be active during reset.
THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while a high
level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not affected by
this signal.
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure determin-
istic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
If JTAG is not used, this pin must be connected to ground.
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal pull-
up resistor.
If JTAG is not used, this pin may be left unconnected.
TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while the
data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-state devices
contained in the test logic will retain their state indefinitely.
If JTAG is not used, this pin may be left unconnected.
TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test logic.
The data on TDO is clocked out of the device on the falling edge of TCK.
If JTAG is not used, this pin should be left unconnected.
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI is
clocked into the device on the rising edge of TCK.
If JTAG is not used, this pin may be left unconnected.
3.3 V I/O power supply
I/O ground
00 = JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10 = JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
Power Supplies and Grounds
JTAG Signals
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
16
Description
December 12, 2005