82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 45
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82V2042EPF8
Manufacturer Part Number
82V2042EPF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V2042EPF8.pdf
(83 pages)
Specifications of 82V2042EPF8
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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4.3.2
Table-25 TERM: Transmit and Receive Termination Configuration Register
4.3.3
Table-26 JACF: Jitter Attenuation Configuration Register
PROGRAMMING INFORMATION
IDT82V2042E
R_TERM[2:0]
T_TERM[2:0]
JACF[1:0]
JADP[1:0]
JA_LIMIT
Symbol
Symbol
JABW
TRANSMIT AND RECEIVE TERMINATION REGISTER
JITTER ATTENUATION CONTROL REGISTER
-
-
(R/W, Address = 03H, 23H)
(R/W, Address = 02H, 22H)
7-6
5-3
2-0
7-6
4-3
2-1
Bit
Bit
5
0
Default
Default
000
000
00
00
00
00
1
0
Reserved.
These bits select the internal termination for transmit line impedance matching.
= 000: Internal 75 Ω impedance matching
= 001: Internal 120 Ω impedance matching
= 010: Internal 100 Ω impedance matching
= 011: Internal 110 Ω impedance matching
= 1xx: Selects external impedance matching resistors for E1 mode only. T1/J1 does not require external impedance
resistors (see Table-10).
These bits select the internal termination for receive line impedance matching.
= 000: Internal 75 Ω impedance matching
= 001: Internal 120 Ω impedance matching
= 010: Internal 100 Ω impedance matching
= 011: Internal 110 Ω impedance matching
= 1xx: Selects external impedance matching resistors (see Table-11).
Reserved.
= 0: Normal mode
= 1: JA limit mode
Jitter Attenuation configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
Jitter Attenuation depth select
= 00: 128 bits
= 01: 64 bits
= 1x: 32 bits
Jitter transfer function bandwidth select
= 0: 6.8 Hz (E1)
= 1: 0.9 Hz (E1)
5 Hz (T1/J1)
1.25 Hz (T1/J1)
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
45
Description
Description
December 12, 2005
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