82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 61

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

6
described in the IEEE 1149.1 standards.
ters plus a Test Access Port (TAP) controller. Control of the TAP is per-
formed through signals applied to the Test Mode Select (TMS) and Test
Clock (TCK) pins. Data is shifted into the registers via the Test Data Input
IEEE STD 1149.1 JTAG TEST ACCESS PORT
IDT82V2042E
The IDT82V2042E supports the digital Boundary Scan Specification as
The boundary scan architecture consists of data and instruction regis-
IEEE STD 1149.1 JTAG TEST ACCESS PORT
TRST
TDI
TCK
TMS
parallel latched output
Digital output pins
(Test Access Port)
Controller
TAP
IDR (Device Identification Register)
BSR (Boundary Scan Register)
Figure-21 JTAG Architecture
IR (Instruction Register)
BR (Bypass Register)
Control<6:0>
Digital input pins
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
61
(TDI) pin, and shifted out of the registers via the Test Data Output (TDO)
pin. Both TDI and TDO are clocked at a rate determined by TCK.
ister), IDR (Device Identification Register), BR (Bypass Register) and IR
(Instruction Register). These will be described in the following pages. Refer
to
Figure-21
The JTAG boundary scan registers include BSR (Boundary Scan Reg-
for architecture.
high impedance enable
Select
MUX
December 12, 2005
TDO