82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 23
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82V2042EPF8
Manufacturer Part Number
82V2042EPF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V2042EPF8.pdf
(83 pages)
Specifications of 82V2042EPF8
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
Table-9 Transmit Waveform Value For J1 0~655 ft
3.3.4
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω, 100 Ω,
110 Ω or 120 Ω internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
Table-10 Impedance Matching for Transmitter
3.3.5
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0]
results in 2% scaling up/down against the pulse amplitude.
FUNCTIONAL DESCRIPTION
IDT82V2042E
The transmit line interface consists of TTIPn and TRINGn pins. The
Note: The precision of the resistors should be better than ± 1%
The transmit path can be powered down individually by setting the
Sample
10
12
13
14
15
16
11
Cable Configuration
1
2
3
4
5
6
7
8
9
TRANSMIT PATH LINE INTERFACE
TRANSMIT PATH POWER DOWN
T1/133~266 ft
T1/266~399 ft
T1/399~533 ft
T1/533~655 ft
T1/0~133 ft
J1/0~655 ft
E1/120 Ω
E1/75 Ω
0100110
0100101
0100101
0100101
0100100
0100011
1001010
1001010
1001001
1000101
1000100
1000011
0010111
0100111
0100111
1000111
UI 1
1000010
1000001
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
UI 2
T_TERM[2:0]
000
001
010
011
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
UI 3
Internal Termination
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
PULS[3:0]
UI 4
0000
0001
0010
0011
0100
0101
0110
0111
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
23
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
the cable for one channel.
ance matching for transmitter.
matching for both receiver and transmitter on a per channel basis. If TERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used in E1 mode, or external imped-
ance network for receiver and internal impedance network for transmitter
will be used in T1/J1 mode. (This applies to ZB die revision only). When
internal impedance network is used, PULSn[3:0] pins should be set to
select the specific internal impedance in the corresponding channel. Refer
to
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
impedance globally by pulling THZ pin to high. Refer to
TROL PIN SUMMARY
impedance:
•
•
•
•
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to
WARE CONTROL PIN SUMMARY
0 Ω
R
5 HARDWARE CONTROL PIN SUMMARY
Figure-8
In hardware control mode, TERMn pin can be used to select impedance
The TTIPn/TRINGn can also be turned into high impedance globally by
In hardware control mode, TTIPn/TRINGn pins can be turned into high
Besides, in the following cases, TTIPn/TRINGn will also become high
In hardware control mode, the transmit path can be powered down by
T
Loss of MCLK;
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
shows the appropriate external components to connect with
T_TERM[2:0]
1XX
-
for details.
Table-10
External Termination
for details.
is the list of the recommended imped-
PULS[3:0]
0001
0001
for details.
-
December 12, 2005
5 HARDWARE CON-
9.4 Ω
R
-
T
5 HARD-