82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 40

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.13 INTERRUPT HANDLING
When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active
low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 20H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
the INTM_GLB bit (GCF, 20H) is set to ‘0’, an active level on the INT pin
represents an interrupt of the IDT82V2042E. The INT_CH[1:0] (GCF, 20H)
should be read to identify which channel(s) generate the interrupt.
Status Register (INTS0, 18H...) or (INTS1, 19H...). Every kind of interrupt
can be enabled/disabled individually by the corresponding bit in the register
(INTM0, 13H...) or (INTM1, 14H...). Some event is reflected by the corre-
sponding bit in the Status Register (STAT0, 16H...) or (STAT1, 17H...), and
the Interrupt Trigger Edge Selection Register can be used to determine how
the Status Register sets the Interrupt Status Register.
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (21H) will be reset. Only when all the pending
Table-18 Interrupt Event
Arbitrary Waveform Generator
FUNCTIONAL DESCRIPTION
IDT82V2042E
Inband Loopback Deactivate Code Status
Synchronization Status of PRBS/QRSS
Inband Loopback Activate Code Status
All kinds of interrupt of the IDT82V2042E are indicated by the INT pin.
All the interrupt can be disabled by the INTM_GLB bit (GCF, 20H). When
The interrupt event is captured by the corresponding bit in the Interrupt
After the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...) is
One-Second Timer Expired
Excessive Zeros Received
Code Violation Received
Error Counter Overflow
Driver Failure Detected
JA FIFO Underflow
PRBS/QRSS Error
JA FIFO Overflow
Interrupt Event
LOS Detected
AIS Detected
TCLK Loss
Overflow
(STAT0, STAT1)
TCLK_LOS
Status bit
IBLBA_S
IBLBD_S
PRBS_S
LOS_S
AIS_S
DF_S
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
40
Interrupt Status bit
(INTS0, INTS1)
TCLK_LOS_IS
interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 18H...) or (INTS1, 19H...) will all the bits in the
INTCH register (21H) be reset and the INT pin become inactive.
source for one channel:
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
CNT_OV_IS
DAC_OV_IS
IBLBD_IS
TMOV_IS
IBLBA_IS
PRBS_IS
JAOV_IS
JAUD_IS
ERR_IS
LOS_IS
EXZ_IS
There are totally thirteen kinds of events that could be the interrupt
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).One-Second Timer Expired
(12). Error Counter Overflow
(13).Arbitrary Waveform Generator Overflow
Table-18
AIS_IS
DF_IS
CV_IS
is a summary of all kinds of interrupt and the associated Status
Interrupt Edge Selection
IBLBD_IES
PRBS_IES
IBLBA_IES
TCLK_IES
LOS_IES
AIS_IES
(INTES)
DF_IES
bit
December 12, 2005
Interrupt Mask bit
(INTM0, INTM1)
DAC_OV_IM
TIMER_IM
IBLBA_IM
IBLBD_IM
PRBS_IM
TCLK_IM
JAOV_IM
JAUD_IM
ERR_IM
CNT_IM
LOS_IM
EXZ_IM
AIS_IM
DF_IM
CV_IM