82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 29

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.6
3.6.1
nal level and pulse density of the received signal on RTIPn and RRINGn.
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0CH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0CH...). LOS status is cleared by pulling LOSn pin to low.
FUNCTIONAL DESCRIPTION
IDT82V2042E
(observing windows= M)
The Loss of Signal Detector monitors the amplitude of the incoming sig-
• LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
• LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
density=OK
signal level>P
LOS AND AIS DETECTION
LOS DETECTION
Figure-13 LOS Declare and Clear
LOS=0
LOS=1
(observing windows= N)
signal level<Q
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
29
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hys-
teresis).
LOS[4:0] bit (RCF1, 0AH...), while P=Q+4 dB (4 dB is the LOS level detect
hysteresis). Refer to Table 33, “RCF1: Receiver Configuration Register 1,”
on page 48 for LOS[4:0] bit values available.
not be enabled and Programmable LOS levels are not available (pin 58 &
pin 60 have to be set to ‘0’).
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT0, 0CH...) and T1E1 bit (GCF, 20H).
both with and without the Adaptive Equalizer enabled.
tion” at the RTIPn/RRINGn side and output recovered clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
the maximum receive sensitivity) when AISE bit (MAINT0, 0CH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0CH...) is 1. In this case
RCLKn output is replaced by MCLK.
ATAO bit (MAINT0, 0CH...) is 1. The All Ones pattern uses MCLK as the
reference clock.
• LOS detect level threshold
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
With the Adaptive Equalizer on, the value of Q can be selected by
When the chip is configured by hardware, the Adaptive Equalizer can
• Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1
Table-13
• All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
On the line side, the TTIPn/TRINGn will output All Ones as AIS when
LOS indicator is always active for all kinds of loopback modes.
and
Table-14
summarize LOS declare and clear criteria for
December 12, 2005
/J1
mode and