82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 26

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.4.3
tivity and to allow programming of the LOS level up to -24 dB. See section
3.6 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
3.4.4
With the Adaptive Equalizer enabled, the receive sensitivity will be -20 dB.
receive sensitivity is fixed at -10 dB for both E1 and T1/J1. Refer to
WARE CONTROL PIN SUMMARY
3.4.5
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...). The output of the Data Slicer is forwarded to the CDR (Clock & Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.4.6
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.4.7
select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0]
bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder.
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to
FUNCTIONAL DESCRIPTION
IDT82V2042E
The Adaptive Equalizer can be enabled to increase the receive sensi-
In Host mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB.
In Hardware mode, the Adaptive Equalizer can not be enabled and the
The Data Slicer is used to generate a standard amplitude mark or a
The CDR is used to recover the clock and data from the received signal.
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to
When the chip is configured by hardware, the operation mode of receive
ADAPTIVE EQUALIZER
RECEIVE SENSITIVITY
DATA SLICER
CDR (Clock & Data Recovery)
DECODER
5 HARDWARE CONTROL PIN SUMMARY
for details.
for details.
5 HARD-
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
26
3.4.8
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
selected. If RCLKE is set to high, the falling edge will be chosen as the active
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR) of the RDPn and RDNn. This is called receiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
3.4.9
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
ing RPDn pin to high on a per channel basis. Refer to
TROL PIN SUMMARY
The receive path system interface consists of RCLKn pin, RDn/RDPn
In hardware control mode, only the active edge of RCLKn can be
The received data can be output to the system side in two different ways:
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
The receive path can be powered down individually by setting R_OFF
In hardware control mode, receiver power down can be selected by pull-
RECEIVE PATH SYSTEM INTERFACE
RECEIVE PATH POWER DOWN
for more details.
December 12, 2005
5 HARDWARE CON-