82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 38

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.11 MCLK AND TCLK
3.11.1 MASTER CLOCK (MCLK)
MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock
is used to generate several internal reference signals:
•
•
•
•
•
•
MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to
high impedance state.
FUNCTIONAL DESCRIPTION
IDT82V2042E
MCLK is an independent, free-running reference clock. MCLK is 1.544
Figure-19
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during Transmit All Ones (TAOS), all zeros, PRBS/
QRSS and Inband Loopback code if it is selected as the reference
clock. For ATAO and AIS, MCLK is always used as the reference
clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS/QRSS in hardware
shows the chip operation status in different conditions of
both the transmitters high
impedance
MCLK=H/L?
control
yes
mode.
Figure-19 TCLK Operation Flowchart
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter n high impedance
Clocked
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
38
L/H
3.11.2 TRANSMIT CLOCK (TCLK)
active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...).
During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback
Code, either TCLKn or MCLK can be used as the reference clock. This is
selected by the PATT_CLK bit (MAINT0, 0CH...).
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0CH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0CH) is set to ‘1’.
bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
is not using MCLK to transmit internal patterns (TAOS, All Zeros, PRBS and
in-band loopback code). When TCLK is detected again, TCLK_LOS bit
(STAT0, 16H...) will be cleared. The reference frequency to detect a TCLK
loss is derived from MCLK.
TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
TCLKn status?
normal operation
clocked
December 12, 2005