82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 62

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

6.1
select the test to be executed or the data register to be accessed or both.
52
Table-52 Instruction Register Description
6.2
6.2.1
device revision, which can be used to verify the proper version or revision
number that has been used in the system under test. The IDR is 32 bits long
and is partitioned as in Table-53. Data from the IDR is shifted out to TDO
LSB first.
Table-53 Device Identification Register Description
IEEE STD 1149.1 JTAG TEST ACCESS PORT
IDT82V2042E
for details of the codes and the instructions related.
The IR (Instruction Register) with instruction decode block is used to
The instructions are shifted in LSB first to this 3-bit register. See
The IDR can be set to define the producer number, part number and the
IR CODE
Bit No.
12-27
28-31
1-11
JTAG INSTRUCTIONS AND INSTRUCTION REG-
000
100
JTAG DATA REGISTER
DEVICE IDENTIFICATION REGISTER (IDR)
110
111
ISTER
0
Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
INSTRUCTION
Bypass
Idcode
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST
instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by load-
ing the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary
scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through
input TDI into the boundary scan register using the Update-DR state.
between TDI and TDO. The normal path between
and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then
be viewed by shifting the boundary scan register using the Shift-DR state.
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification
code can then be shifted out using the Shift-DR state.
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to
bypass the device.
Producer Number
Device Revision
Comments
Part Number
Set to ‘1’
Table-
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
62
6.2.2
TDI input and TDO output, bypassing the BSR to reduce test access times.
6.2.3
digital I/O pins. The BSR is a 98 bits long shift register and is initialized and
read using the instruction EXTEST or SAMPLE/PRELOAD. Each pin is
related to one or more bits in the BSR. For details, please refer to the BSDL
file.
6.2.4
shows its state diagram following the description of each state. Note that
the figure contains two main branches to access either the data or instruc-
tion registers. The value shown next to each state transition in this figure
states the value present at TMS at each rising edge of TCK. Please refer
to
Table-54
The BR consists of a single bit. It can provide a serial path between the
The BSR can apply and read test patterns in parallel to or from all the
The TAP controller is a 16-state synchronous state machine.
IDT82V2042E
BYPASS REGISTER (BR)
BOUNDARY SCAN REGISTER (BSR)
TEST ACCESS PORT CONTROLLER
COMMENTS
for details of the state description.
logic and the I/O pins is maintained. Primary device inputs
December 12, 2005
Figure-22