82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 49
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82V2042EPF8
Manufacturer Part Number
82V2042EPF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V2042EPF8.pdf
(83 pages)
Specifications of 82V2042EPF8
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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Table-34 RCF2: Receiver Configuration Register 2
4.3.6
Table-35 MAINT0: Maintenance Function Control Register 0
PROGRAMMING INFORMATION
IDT82V2042E
PATT_CLK
PRBS_INV
SLICE[1:0]
PATT[1:0]
Symbol
MG[1:0]
Symbol
ATAO
AISE
LAC
NETWORK DIAGNOSTICS CONTROL REGISTERS
-
-
-
(R/W, Address = 0BH, 2BH)
(R/W, Address = 0CH, 2CH)
7-6
5-4
3-2
1-0
6-5
Bit
Bit
7
4
3
2
1
0
Default
Default
00
01
10
00
00
0
0
0
0
0
0
Reserved.
Receive slicer threshold
= 00: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 40% of the peak amplitude.
= 01: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 50% of the peak amplitude.
= 10: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 60% of the peak amplitude.
= 11: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 70% of the peak amplitude.
Reserved
Monitor gain setting: these bits select the internal linear gain boost
= 00: 0 dB
= 01: 22 dB
= 10: 26 dB
= 11: 32 dB
Reserved.
These bits select the internal pattern and insert it into transmit data stream.
= 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)
= 01: Insert All Ones
= 10: Insert PRBS (E1: 2
= 11: Insert programmable Inband loopback activate or deactivate code (default value 00001)
Selects reference clock for transmitting internal pattern
= 0: Uses TCLKn as the reference clock
= 1: Uses MCLK as the reference clock
Inverts PRBS
= 0: The PRBS data is not inverted
= 1: The PRBS data is inverted before transmission and detection
LOS/AIS criterion is selected as below:
= 0: G.775 (E1) / T1.231 (T1/J1)
= 1: ETSI 300233& I.431 (E1) / I.431 (T1/J1)
AIS enable during LOS
= 0: AIS insertion on RDPn/RDNn/RCLKn is disabled during LOS
= 1: AIS insertion on RDPn/RDNn/RCLKn is enabled during LOS
Automatically Transmit All Ones (enabled only when PATT[1:0] = 00)
= 0: Disabled
= 1: Automatically Transmit All Ones pattern at TTIPn/TRINGn during LOS
15
-1) or QRSS (T1/J1: 2
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
49
20
Description
Description
-1)
December 12, 2005
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