82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 48

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

4.3.5
Table-32 RCF0: Receiver Configuration Register 0
Table-33 RCF1: Receiver Configuration Register 1
PROGRAMMING INFORMATION
IDT82V2042E
RCLK_SEL
R_MD[1:0]
LOS[4:0]
RD_INV
Symbol
Symbol
EQ_ON
R_OFF
RECEIVE PATH CONTROL REGISTERS
-
-
-
(R/W, Address = 09H, 29H)
(R/W, Address= 0AH, 2AH)
7-5
1-0
Bit
Bit
4:0
4
3
2
7
6
5
Default
Default
10101
000
00
0
0
0
0
0
0
Reserved
= 0: Receive equalizer off
= 1: Receive equalizer on (LOS programming enabled)
Reserved.
Reserved
Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
Receive data invert
= 0: Data on RDn or RDPn/RDNn is active high
= 1: Data on RDn or RDPn/RDNn is active low
Receive clock edge select (this bit is ignored in slicer mode)
= 0: Data on RDn or RDPn/RDNn is updated on the rising edge of RCLKn
= 1: Data on RDn or RDPn/RDNn is updated on the falling edge of RCLKn
Receive path decoding selection
= 00: Receive data is HDB3 (E1)/B8ZS (T1/J1) decoded and output on RDn pin with single rail NRZ format
= 01: Receive data is AMI decoded and output on RDn pin with single rail NRZ format
= 10: Decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with clock
recovery)
= 11: CDR and decoder are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
01011 - 11111
00000
00001
00010
00100
00101
01000
01001
01010
00011
00110
00111
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
48
LOS Clear Level (dB)
0
>-2
>-4
>-8
>-12
>-14
Reserved
>-6
>-10
>-16
>-18
>-20
Description
Description
LOS Declare Level (dB)
<-4
<-6
<-8
<-10
<-12
<-14
<-16
<-18
<-20
<-22
<-24
December 12, 2005