NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 205

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.20.7.4
5.20.7.5
5.20.8
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
ACPI System States
The EHC behavior as it relates to other power management states in the system is summarized in
the following list:
Mobile Considerations
The ICH6 USB 2.0 implementation does not behave differently in the mobile configurations versus
the desktop configurations. However, some features may be especially useful for the mobile
configurations.
Interaction with UHCI Host Controllers
The Enhanced Host controller shares the eight USB ports with four UHCI Host controllers in the
ICH6. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the UHC
at D29:F2 shares ports 4 and 5; and the UHC at D29:F3 shares ports 6 and 7 with the EHC. There
is very little interaction between the Enhanced and the UHCI controllers other than the
multiplexing control which is provided as part of the EHC.
Connections at a conceptual level.
•
•
•
If a system (e.g., mobile) does not implement all eight USB 2.0 ports, the ICH6 provides
mechanisms for changing the structural parameters of the EHC and hiding unused UHCI
controllers. See ICH6 BIOS Specification on how BIOS should configure the ICH6.
Mobile systems may want to minimize the conditions that will wake the system. The ICH6
implements the “Wake Enable” bits in the Port Status and Control registers, as specified in the
EHCI spec, for this purpose.
Mobile systems may want to cut suspend well power to some or all USB ports when in a
low-power state. The ICH6 implements the optional Port Wake Capability Register in the EHC
Configuration Space for this platform-specific information to be communicated to software.
— The System is always in the S0 state when the EHC is in the D0 state. However, when the
— When in D0, the Pause feature (See
— The PLL in the EHC is disabled when entering the S3
— All core well logic is reset in the S3/S4/S5 states.
EHC is in the D3 state, the system may be in any power management state (including S0).
power states to be entered.
the S3
COLD
/S4/S5 states (core power turns off).
Section
5.20.7.1) enables dynamic processor low-
Figure 5-10
HOT
state (48 MHz clock stops), or
Functional Description
shows the USB Port
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