NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 458

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.1.4
12.1.5
458
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS — PCI Status Register (SATA–D31:F2)
Address Offset:
Default Value:
effect.
RID—Revision Identification Register (SATA—D31:F2)
Offset Address:
Default Value:
10:9
Bit
7:0
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Revision ID — RO. Refer to the Intel
the value of the Revision ID Register
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
Reserved as 0 — RO.
Signaled Target Abort (STA) — RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED) — RO. For ICH6, this bit can only be set on read completions
received from SiBUS where there is a parity error.
1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted,
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 1.
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The
minimum requirement for the capabilities list must be PCI power management for the SATA
controller.
Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register
1 = Interrupt is to be asserted
Reserved
and the parity error response bit (bit 6 of the command register) is set.
[offset 04h]).
06
02B0h
08h
See bit description
–
07h
®
I/O Controller Hub 6 (ICH6) Family Specification Update for
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
R/WC, RO
16 bits
RO
8 bits