NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 260

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.31
7.1.32
7.1.33
260
CSIR7—Chipset Initialization Register 7
Offset Address:
Default Value:
TRSR—Trap Status Register
Offset Address:
Default Value:
TRCR—Trapped Cycle Register
Offset Address:
Default Value:
This register saves information about the I/O Cycle that was trapped and generated the SMI# for
software to read.
63:25
23:20
19:16
31:1
31:4
15:2
Bit
Bit
3:0
Bit
1:0
24
0
Reserved
Chipset Initialization Register 7 Bit[0] — R/W. BIOS sets this bit to 1.
Reserved
Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped).
These bits are OR’ed together to create a single status bit in the Power Management register
space.
Note that the SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby guaranteeing
that the processor can enter the SMI# handler when the instruction completes. Each status bit is
cleared by writing a 1 to the corresponding bit location in this register.
Reserved
Read/Write# (RWI) — RO.
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
Reserved
Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables associated
with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in
the cycle.
Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the trapped cycle.
Reserved
1D40–1D43h
00000000h
1E00–1E03h
00000000h
1E10–1E17h
0000000000000000h
Intel
®
Description
Description
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
32-bit
R/WC, RO
32-bit
RO
64-bit
R/W