NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 89
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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Compliant
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3.4
Intel
Table 3-5. Power Plane for Input Signals for Desktop Configurations (Sheet 1 of 3)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Power Planes for Input Signals
Table 3-5
device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
PERp[1], PERn[1]
PERp[2], PERn[2]
PERp[3], PERn[3]
PERp[4], PERn[4]
ACZ_SDIN[2:0]
ACZ_SDIN[2:0]
Definition Audio
ACZ_BIT_CLK
(AC ‘97 Mode)
(AC ‘97 Mode)
Signal Name
DMI_CLKP,
DMI_CLKN
(Intel High
A20GATE
DDREQ
EE_DIN
GPI[12]
GPI[13]
FERR#
CLK14
CLK48
Mode)
GPI[6]
GPI[7]
GPI[8]
and
Table 3-6
Power Well
VccSus3_3
VccSus3_3
VccSus3_3
V_CPU_IO
VccSus3_3
VccSus3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
shows the power plane associated with each input signal, as well as what
External Device or External
External Device or External
External Device or External
External Device or External
External Device or External
Intel High Definition Audio
External Microcontroller
EEPROM Component
Driver During Reset
PCI Express* Device
Pull-up/Pull-down
Pull-up/Pull-down
Pull-up/Pull-down
Pull-up/Pull-down
Pull-up/Pull-down
Clock Generator
Clock Generator
Clock Generator
AC ’97 Codec
AC ’97 Codec
IDE Device
Processor
Codec
Running
Running
Running
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Static
Static
Static
Low
Low
Low
S1
S3
Driven
Driven
Driven
Driven
Driven
Low
Low
Low
Low
Low
Low
Low
Low
Low
COLD
Off
Off
1
Pin States
Driven
Driven
Driven
Driven
Driven
S4/S5
Low
Low
Low
Low
Low
Low
Low
Low
Low
Off
Off
89
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