NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 48

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Introduction
48
Serial ATA (SATA) Controller
The ICH6 has an integrated SATA host controller that supports independent DMA operation on
four ports (desktop only) or two ports (mobile only) and supports data transfer rates of up to
1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation; a legacy mode using
I/O space, and an AHCI mode using memory space (ICH6R/ICH6-M only).
SATA and PATA can also be used in a combined function mode (where the SATA function is used
with PATA). In this combined function mode, AHCI mode is not used. Software that uses legacy
mode will not have AHCI capabilities.
The ICH6 supports the Serial ATA Specification, Revision 1.0a. The ICH6 also supports several
optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0
(AHCI support is required for some elements).
AHCI (Intel
The ICH6R/ICH6-M provide hardware support for Advanced Host Controller Interface (AHCI), a
new programming interface for SATA host controllers. Platforms supporting AHCI may take
advantage of performance features such as no master/slave designation for SATA devices—each
device is treated as a master—and hardware-assisted native command queuing. AHCI also
provides usability enhancements (e.g., Hot-Plug). AHCI requires appropriate software support
(e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional
platform hardware.
PCI Interface
The ICH6 PCI interface provides a 33 MHz, Revision 2.3 implementation. All PCI signals are 5 V
tolerant, except PME#. The ICH6 integrates a PCI arbiter that supports up to seven external PCI
bus masters in addition to the internal ICH6 requests. This allows for combinations of up to seven
PCI down devices and PCI slots.
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to two IDE devices providing an interface for IDE hard disks
and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports
PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up 100 MB/sec. It does not consume
any legacy DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.
The ICH6’s IDE system contains a single, independent IDE signal channel that can be electrically
isolated. There are integrated series resistors on the data and control lines (see
details).
Low Pin Count (LPC) Interface
The ICH6 implements an LPC Interface as described in the LPC 1.1 specification. The Low Pin
Count (LPC) bridge function of the ICH6 resides in PCI Device 31:Function 0. In addition to the
LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt
controllers, timers, power management, system management, GPIO, and RTC.
®
ICH6R/ICH6-M only)
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Section 5.16
for