NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 682

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
19.1.9
19.1.10
19.1.11
19.1.12
682
CLS—Cache Line Size Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
PLT—Primary Latency Timer Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
HEADTYP—Header Type Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
BNUM—Bus Number Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
23:16
15:8
Bit
7:0
Bit
7:3
2:0
Bit
6:0
Bit
7:0
7
Base Class Code (BCC) — R/W. This is read/write but contains no functionality, per the PCI*
Express Base Specification .
Latency Count. Reserved per the PCI Express* Base Specification.
Reserved
Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
Configuration Layout. Hardwired to 01h, which indicates a PCI-to-PCI bridge.
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the
bridge.
Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port.
Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone.
0Ch
00h
0Dh
00h
0Eh
81h
18–1Ah
000000h
Intel
Description
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
RO
24 bits
R/W
8 bits
8 bits
8 bits
R/W