NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 393

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.8
10.8.1
Intel
Table 10-9. Power Management PCI Register Address Map (PM—D31:F0)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
Power Management PCI Configuration Registers
(PM—D31:F0)
Table 10-9
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
B8–BBh
Offset
ABh
ADh
A0h
A2h
A4h
AAh
A9h
shows a small part of the configuration space for PCI Device 31: Function 0. It includes
C4-TIMING_CNT
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
Cx-STATE_CNF
BM_BREAK_EN
GPI_ROUT
Mnemonic
MSC_FUN
General Power Management Configuration 1
General Power Management Configuration 2
General Power Management Configuration 3
Cx State Configuration (Mobile Only).
C4 Timing Control (Mobile Only).
BM_BREAK_EN
Miscellaneous Functionality
GPI Route Control
Register Name
LPC Interface Bridge Registers (D31:F0)
00000000h
Default
0000h
00h
00h
00h
00h
00h
00h
R/W, R/WC
R/W, R/WC
R/W, RO,
R/WO
Type
R/W
R/W
R/W
R/W
R/W
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