NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 635

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

18.1.19
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
HDCTL—Intel
(Intel
Address Offset:
Default Value:
Bit
7:4
3
2
1
0
®
Reserved.
BITCLK Detect Clear (CLKDETCLR) — R/W.
0 = When a 0 is written to this bit, the clock detect circuit is operational and maybe enabled.
1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains clear when
this bit is set to 1.
NOTE: This bit is not affected by the D3
BITCLK Detect Enable (CLKDETEN) — R/W.
0 = Latches the current state of bit 1 (CLKDET#) in this register
1 = Enables the clock detection circuit
NOTE: This bit is not affected by the D3
BITCLK Detected Inverted (CLKDET#) — RO. This bit is modified by hardware.
It is set to 0 when the Intel
AC ’97 codec on the link.
NOTES:
Intel High Definition Audio/AC ‘97 Signal Mode — R/W. This bit selects the shared Intel High
Definition Audio/AC ‘97 signals.
0 = AC ’97 mode is selected (Default)
1 = Intel High Definition Audio mode is selected
NOTES:
1. Bit 2 (CLKDETEN) and bit 3 (CLKDETCLR) in this register control the operation of this bit and
2. This bit is not affected by the D3
1. This bit has no affect on the visibility of the Intel High Definition Audio and AC ’97 function
2. This bit is in the resume well and only clear on a power-on reset. Software must not makes
High Definition Audio Controller—D27:F0)
must be manipulated correctly in order to get a valid CLKDET# indicator.
configuration space.
assumptions about the reset state of this bit and must set it appropriately.
40h
00h
®
High Definition Audio Control Register
Intel
®
ICH6 detects that the BITCLK is toggling, indicating the presence of an
®
High Definition Audio Controller Registers (D27:F0)
HOT
to D0 transition.
HOT
HOT
Description
to D0 transition.
to D0 transition.
Attribute:
Size:
R/W, RO
8 bits
635