NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 461

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.1.9
12.1.10
.
12.1.11
.
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset:
Default Value:
PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)
Address Offset:
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2)
Address Offset:
Default Value:
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:16
31:16
15:3
15:2
Bit
2:1
Bit
Bit
7:0
0
1
0
Reserved
Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (4 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
Master Latency Timer Count (MLTC) — RO. The SATA controller is implemented internally, and is
not arbitrated as a PCI device, so it does not need a Master Latency Timer.
00h = Hardwired.
0Dh
00h
10h
00000001h
14h
00000001h
–
–
13h
17h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
RO
8 bits
R/W, RO
32 bits
R/W, RO
32 bits
461