FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 169
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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®
Table 73. Heartbeat Message Data
82801EB ICH5 / 82801ER ICH5R Datasheet
Once the system transitions to the non-S0 state, it may send a single alert with an incremental
SEQUENCE number.
Table 73
Cover Tamper Status
Temp Event Status
Processor Missing Event
Status
TCO Timer Event Status
Software Event Status
Unprogrammed Flash
BIOS Event Status
GPIO Status
SEQ[3:0]
System Power State
MESSAGE1
MESSAGE2
WDSTATUS
5. An inaccurate alert message can be generated in the following scenario
— The system successfully boots after a second watchdog Timeout occurs.
— PWROK goes low (typically due to a reset button press) or a power button override
— An alert message indicating that the Processor is missing or locked up is generated with a
occurs (before the SECOND_TO_STS bit is cleared).
new sequence number.
shows the data included in the Alert on LAN messages.
Field
1 = This bit is set if the intruder detect bit is set (INTRD_DET).
1 = This bit is set if the Intel
1 = This bit is set if the processor failed to fetch its first instruction.
1 = This bit is set when the TCO timer expires.
1 = This bit is set when software writes a 1 to the SEND_NOW bit.
1 = First BIOS fetch returned a value of FFh, indicating that the flash BIOS has
not yet been programmed (still erased).
1 = This bit is set when GPIO11 signal is high.
0 = This bit is cleared when GPIO11 signal is low.
An event message is triggered on an transition of GPIO11.
This is a sequence number. It initially is 0, and increments each time the ICH5
sends a new message. Upon reaching 1111, the sequence number rolls over to
0000. MSB (SEQ3) sent first.
00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first
Will be the same as the MESSAGE1 Register. MSB sent first.
Will be the same as the MESSAGE2 Register. MSB sent first.
Will be the same as the WDSTATUS Register. MSB sent first.
®
ICH5 THERM# input signal is asserted.
Comment
Functional Description
169
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