FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 232
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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Functional Description
5.21.1.1
232
Table 103. Quick Protocol
Table 104. Send / Receive Byte Protocol without PEC
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the
progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the
command completes successfully, the INTR bit will be set in the Host Status Register. If the device
does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If
software sets the KILL bit in the Host Control Register while the command is running, the
transaction will stop and the FAILED bit will be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC
byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when
performing the Quick Command. Software must force the I2C_EN bit to 0 when running this
command.The format of the protocol is shown in
Send Byte / Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent
For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is
stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this
command.
The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. The
format of the protocol is shown in
18:11
8:2
Bit
10
19
20
1
9
Bit
8:2
10
11
1
9
Start
Slave Address — 7 bits
Write
Acknowledge from slave
Command code — 8 bits
Acknowledge from slave
Stop
Send Byte Protocol
Start Condition
Slave Address — 7 bits
Read / Write Direction
Acknowledge from slave
Stop
Description
Description
Table
104. and
Intel
Table
Table
18:11
®
Bit
8:2
19
10
20
1
9
82801EB ICH5 / 82801ER ICH5R Datasheet
103.
105.
Start
Slave Address — 7 bits
Read
Acknowledge from slave
Data byte from slave
NOT Acknowledge
Stop
Receive Byte Protocol
Description
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