FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 77
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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Intel
Domains
Intel
®
Table 30. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
®
Table 30
system components, including the clock generator. For complete details of the system clocking
solution, refer to the system’s clock generator component specification.
ICH5 and System Clock
Clock Domain
AC_BIT_CLK
System PCI
LAN_CLK
CLK100
PCICLK
CLK66
CLK48
CLK14
®
ICH5
ICH5
ICH5
ICH5
ICH5
ICH5
ICH5 and System Clock Domains
shows the system clock domains.
14.31818 MHz
12.288 MHz
5 to 50 MHz
Frequency
100 MHz
66 MHz
33 MHz
48 MHz
33 MHz
AC ’97 Codec
LAN Connect
Component
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Generator
Generator
Generator
Generator
Generator
Generator
Source
Figure 4
Differential clock pair used for SATA.
Hub I/F, Processor I/F. Shut off during S3 or below.
Free-running PCI Clock to the Intel
remains on during S0 and S1 state, and is expected to
be shut off during S3 or below.
PCI Bus, LPC I/F. These only go to external PCI and
LPC devices.
Super I/O, USB controllers. Expected to be shut off
during S3 or below.
Used for ACPI timer and high-precision event timers.
Expected to be shut off during S3 or below.
AC-link. Generated by AC ’97 codec. Can be shut by
codec in D3. Expected to be shut off during S3 or below.
Generated by the LAN Connect component. Expected
to be shut off during S3 or below.
shows the assumed connection of the various
Intel
®
ICH5 and System Clock Domains
Usage
®
ICH5. This clock
4
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