FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 57
FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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Table 11. Interrupt Signals
82801EB ICH5 / 82801ER ICH5R Datasheet
Interrupt Interface
PIRQ[H:E]# /
PIRQ[D:A]#
IRQ[14:15]
GPIO[5:2]
SERIRQ
Name
Type
I/OD
I/OD
I/O
I
Serial Interrupt Request: This pin implements the serial interrupt protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to
interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in
PIRQx# line has a separate Route Control register.
In APIC mode, these signals are connected to the internal I/O APIC in the following
fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and
PIRQD# to IRQ19. This frees the legacy interrupts.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to
interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in
PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the following
fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and
PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts,
these signals can be used as GPIO.
Interrupt Request 14–15: These interrupt inputs are connected to the IDE drives.
IRQ14 is used by the drives connected to the Primary controller and IRQ15 is used
by the drives connected to the Secondary controller.
Description
Signal Description
Section
Section
5.8.6. Each
5.8.6. Each
57
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