FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 566
FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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AC ’97 Modem Controller Registers (D31:F6)
16.1.15
16.1.16
16.1.17
566
INT_LN—Interrupt Line Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.
INT_PIN—Interrupt Pin Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt pin is used for the AC ’97 modem interrupt. The AC ’97
interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
PID—PCI Power Management Capability Identification
Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
15:8
Bit
7:0
Bit
7:3
2:0
Bit
7:0
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel
to software the interrupt line that the interrupt pin is connected to.
Reserved
Interrupt Pin (INT_PN) — RO. Hardwired to 010b to select PIRQB#.
Next Capability (NEXT) — RO. This field indicates that this is the last item in the list.
Capability ID (CAP) — RO. This field indicates that this pointer is a message signaled interrupt
capability.
3Ch
00h
No
3Dh
02h
No
50h
0001h
No
Description
Description
Description
Intel
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5. It is used to communicate
R/W
8 bits
Core
RO
8 bits
Core
RO
16 bits
Core
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