FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 633
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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Intel
®
Table 198. XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks While PWROK Active)
82801EB ICH5 / 82801ER ICH5R Datasheet
It is important to note that the number of inputs pulled to 1 will affect the expected chain output
value. If the number of chain inputs pulled to 1 is even, then expect 1 at the output. If the number of
chain inputs pulled to 1 is odd, expect 0 at the output.
Continuing with the example in
sequence, the XOR Output will toggle between 0 and 1. Any break in the toggling sequence (e.g.,
“1011”) will identify the location of the short or open.
AC_BIT_CLK
AC_SYNC
AC_SDOUT
PIRQE#/GPIO2
GNT2#
REQ3
GNT3#
GNTA#/GPIO16
REQB#/REQ5#/
GPIO1
REQ4#
REQA#/GPIO0
PIRQF#/GPIO3
GNT4#
GNTB#/
GNT5#GPIO17
GNT1#
PIRQC#
PIRQA#
PIRQH#/GPIO5
PIRQD#
REQ1#
REQ2#
AD18
REQ0#
PIRQG#/GPIO4
AD28
PIRQB#
Pin Name
D8
B8
A9
D7
B7
B6
C7
E8
E7
C6
A5
A6
A4
B4
A3
A2
B3
B1
C2
C1
C5
B2
D5
E2
F5
E1
Ball #
Top of XOR Chain
2nd signal in XOR
Table
Notes
197, as the input pins are driven to 1 across the chain in
AD15
GNT0#
AD22
AD30
AD20
AD16
AD4
AD24
AD0
STOP#
AD11
AD26
AD6
TRDY#
FRAME#
AD9
AD2
PAR
AD5
AD13
AD1
SERR#
C/BE0#
C/BE1#
AD3
AD10
TP0
Pin Name
G5
D4
C4
F4
H3
G4
H5
E6
J4
E5
H4
D3
J3
E4
D2
F2
G3
F1
H2
G2
J5
L4
E3
J1
K4
M4
AB2
Ball #
XOR Chain #1
OUTPUT
Notes
Testability
633
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