FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 390
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
- Current page: 390 of 671
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LPC Interface Bridge Registers (D31:F0)
9.10.4
9.10.5
390
PM1_TMR—Power Management 1 Timer Register
I/O Address:
Default Value:
Lockable:
Power Well:
PROC_CNT—Processor Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
31:24
31:18
23:0
16:9
Bit
Bit
17
8
Reserved
Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This counter runs off a
3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then
continues counting as long as the system is in the S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit is
set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit is set, an SCI
interrupt is also generated.
Reserved
Throttle Status (THTL_STS) — RO.
0 = No clock throttling is occurring (maximum processor performance).
1 = Indicates that the clock state machine is in some type of low power state (where the processor
Reserved
Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force the thermal
throttling function. This has the same effect as the THRM# signal being active for 2 seconds.
0 = No forced throttling.
1 = Throttling at the duty cycle specified in THRM_DTY starts immediately (no 2 second delay), and
is not running at its maximum performance): thermal throttling or hardware throttling.
no SMI# is generated.
PMBASE + 08h
( ACPI PMTMR_BLK )
xx000000h
No
Core
PMBASE + 10h
( ACPI P_BLK )
00000000h
No (bits 7:5 are write once)
Core
Intel
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
32-bit
RO
32-bit
ACPI
R/W, RO, WO
ACPI or Legacy
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