FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 374
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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LPC Interface Bridge Registers (D31:F0)
9.7.2
9.7.3
374
Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-Access
NMI_EN—NMI Enable (and Real Time Clock Index) Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Mode. Note, however, that this register is aliased to Port 74h (documented in), and all bits are
readable at that address.
PORT92—Fast A20 and Init Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bits
6:0
Bit
7:2
7
1
0
NMI Enable (NMI_EN) — R/W (special).
0 = Enable NMI sources.
1 = Disable All NMI sources.
Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to the RTC to
select which register or CMOS RAM address is being accessed.
Reserved
Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE input signal to
generate A20M# to the processor.
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the Intel
for 16 PCI clocks.
70h
80h
No
92h
00h
No
Description
Description
Intel
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
R/W (special)
8-bit
Core
R/W
8-bit
Core
ICH5 will force INIT# active
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